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36-mbit (1m x 36/2m x 18/512k x 72) pipelined sram with nobl? architecture CY7C1460AV25 cy7c1462av25 cy7c1464av25 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05354 rev. *d revised june 22, 2006 features ? pin-compatible and functionally equivalent to zbt? ? supports 250-mhz bus operations with zero wait states ? available speed grades are 250, 200 and 167 mhz ? internally self-time d output buffer cont rol to eliminate the need to use asynchronous oe ? fully registered (inputs and outputs) for pipelined operation ? byte write capability ? 2.5v core power supply ? 2.5v/1.8v i/o power supply ? fast clock-to-output times ? 2.6 ns (for 250-mhz device) ? clock enable (cen ) pin to suspend operation ? synchronous self-timed writes ? CY7C1460AV25, cy7c1462av25 available in jedec-standard lead-free 100-pin tqfp package, lead-free and non-lead-free 165-ball fbga package. cy7c1464av25 available in lead-free and non-lead-free 209-ball fbga package ? ieee 1149.1 jtag-compatible boundary scan ? burst capability?linear or interleaved burst order ? ?zz? sleep mode option and stop clock option functional description the CY7C1460AV25/cy7c1462av25/cy7c1464av25 are 2.5v, 1m x 36/2m x 18/512 x 72 synchronous pipelined burst srams with no bus latency? (nobl ?) logic, respectively. they are designed to support unlimited true back-to-back read/write operations with no wait states. the CY7C1460AV25/cy7c1462av25/cy7c1464av25 are equipped with the advanced (nobl) logic required to enable consecutive read/write operations with data being trans- ferred on every clock cycle. this feature dramatically improves the throughput of data in systems that require frequent write/read transitions. the CY7C1460AV25/cy7c1462av25/cy7c1464av25 are pin-compatible and functionally equivalent to zbt devices. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by t he rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previous clock cycle. write oper ations are controlled by the byte write selects (bw a ?bw h for cy7c1464av25, bw a ?bw d for CY7C1460AV25 and bw a ?bw b for cy7c1462av25) and a write enable (we ) input. all writes are conducted with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output three-state co ntrol. in order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b dqp c dqp d d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s e clk c en write drivers bw c bw d zz sleep control o u t p u t r e g i s t e r s logic block diagram?CY7C1460AV25 (1m x 36)
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 2 of 27 selection guide 250 mhz 200 mhz 167 mhz unit maximum access time 2.6 3.2 3.4 ns maximum operating current 435 385 335 ma maximum cmos standby current 120 120 120 ma a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e clk c en write drivers zz sleep control logic block diagram?cy7c1462av25 (2m x 18) a0, a1, a c mode ce1 ce2 ce3 oe read logic dq s dq p a dq p b dq p c dq p d dq p e dq p f dq p g dq p h d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e c lk c en write drivers bw a bw b we zz sleep control bw c write registry and data coherency control logic bw d bw e bw f bw g bw h logic block diagram?cy7c1464av25 (512k x 72)
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 3 of 27 pin configurations a a a a a 1 a 0 v ss v dd a a a a a a v ddq v ss dqb dqb dqb v ss v ddq dqb dqb v ss nc v dd dqa dqa v ddq v ss dqa dqa v ss v ddq v ddq v ss dqc dqc v ss v ddq dqc v dd v ss dqd dqd v ddq v ss dqd dqd dqd v ss v ddq a a ce 1 ce 2 bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz CY7C1460AV25 100-pin tqfp pinout a a a a a 1 a 0 v ss v dd a a a a a a a nc nc v dd q v ss nc dqp dqa dqa v ss v dd q dqa dqa v ss nc v dd dqa dqa v dd q v ss dqa dqa nc nc v ss v dd q nc nc nc nc nc nc v ddq v ss nc nc dqb dqb v ss v ddq dqb dqb v dd v ss dqb dqb v ddq v ss dqb dqb dqpb nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode cy7c1462av25 bw d mode bw c dqc dqc dqc dqc dqpc dqd dqd dqd dqpb dqb dqa dqa dqa dqa dqpa dqb dqb (1m 36) (2m 18) bw b nc nc nc dqc nc nc/288m nc/144m nc/72m nc/288m nc/144m nc/72m dqpd a a a a
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 4 of 27 pin configurations (continued) 234 567 1 a b c d e f g h j k l m n p r tdo nc/576m nc/1g dqp c dq c dqp d nc dq d a ce 1 bw b ce 3 bw c cen a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc/72m v ddq bw d bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc/144m nc v ddq v ss tms 891011 nc/288m a a adv/ld nc oe a a nc v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a 234 567 1 a b c d e f g h j k l m n p r tdo nc/576m nc/1g nc nc dqp b nc dq b a ce 1 ce 3 bw b cen a ce2 nc dq b dq b mode nc dq b dq b nc nc nc nc/72m v ddq bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc/144m nc v ddq v ss tms 891011 nc/288m a a adv/ld nc a oe a a v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a cy7c1462av25 (2m 18) CY7C1460AV25 (1m 36) 165-ball fbga (15 x 17 x 1.4 mm) pinout a a nc nc
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 5 of 27 pin configurations (continued) a b c d e f g h j k l m n p r t u v w 123456789 11 10 dqg dqg dqg dqg dqg dqg dqg dqg dqc dqc dqc dqc nc dqpg dqh dqh dqh dqh dqd dqd dqd dqd dqpd dqpc dqc dqc dqc dqc nc dqh dqh dqh dqh dqph dqd dqd dqd dqd dqb dqb dqb dqb dqb dqb dqb dqb dqf dqf dqf dqf nc dqpf dqa dqa dqa dqa dqe dqe dqe dqe dqpa dqpb dqf dqf dqf dqf nc dqa dqa dqa dqa dqpe dqe dqe dqe dqe a aa a nc nc nc/144m nc/72m a nc/288m a aa aa a a1 a0 a aa aa a nc/1g nc/576m nc nc nc nc nc bws b bws f bws e bws a bws c bws g bws d bws h tms tdi tdo tck nc nc mode nc cen v ss nc clk nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss v dd nc oe ce 3 ce 1 ce 2 adv/ld we v ss v ss v ss v ss v ss v ss v ss zz v ss v ss v ss v ss nc v ddq v ss v ss nc v ss v ss v ss v ss v ss v ss nc v ss v ddq v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq 209-ball fbga (14 x 22 x 1.76 mm) pinout cy7c1464av25 (512k x 72) pin definitions pin name i/o type pin description a0 a1 a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. bw a bw b bw c bw d bw e bw f bw g bw h input- synchronous byte write select inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bw a controls dq a and dqp a , bw b controls dq b and dqp b , bw c controls dq c and dqp c , bw d controls dq d and dqp d , bw e controls dq e and dqp e, bw f controls dq f and dqp f, bw g controls dq g and dqp g, bw h controls dq h and dqp h . we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input used to advance the on-chip address counter or load a new address . when high (and cen is asserted low) the internal burs t counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input- clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low.
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 6 of 27 ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tri- stated, and act as input data pins. oe is masked during the data portion of a write seq uence, during the first clock when emerging from a deselected state and when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. dq a dq b dq c dq d dq e dq f dq g dq h i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chi p data register that is triggered by the rising edge of clk. as outputs, they del iver the data contained in the memory location specified by a x during the previous clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq a ?dq d are placed in a tri-state condit ion. the outputs are automati- cally tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp a dqp b dqp c dqp d dqp e dqp f dqp g dqp h i/o- synchronous bidirectional data parity i/o lines . functionally, these signals are identical to dq [31:0] . during write sequences, dqp a is controlled by bw a , dqp b is controlled by bw b , dqp c is controlled by bw c , and dqp d is controlled by bw d , dqp e is controlled by bw e , dqp f is controlled by bw f , dqp g is controlled by bw g , dqp h is controlled by bw h . mode input strap pin mode input . selects the burst order of the device. tied high selects the interleaved burst order. pulled low selects the linear burst order. mode should not change states during operation. when left floating mode will default high, to an interleaved burst order. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. tms test mode select synchronous this pin controls the test access port state machine . sampled on the rising edge of tck. tck jtag-clock clock input to th e jtag circuitry . v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device . should be connected to ground of the system. nc n/a no connects . this pin is not connected to the die. nc/72m n/a not connected to the die . can be tied to any voltage level. nc /144m n/a not connected to the die . can be tied to any voltage level. nc /288m n/a not connected to the die . can be tied to any voltage level. nc /576m n/a not connected to the die . can be tied to any voltage level. nc /1g n/a not connected to the die . can be tied to any voltage level. zz input- asynchronous zz ?sleep? input . this active high input places the devic e in a non-time critical ?sleep? condition with data integrity preserved. duri ng normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. pin definitions (continued) pin name i/o type pin description
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 7 of 27 functional overview the CY7C1460AV25/cy7c1462av25/cy7c1464av25 are synchronous-pipelined burst nobl srams designed specifi- cally to eliminate wait states during write/read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 2.6 ns (250-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write operation, depending on the status of the write enable (we ). bw [x] can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clo ck rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the ou tput register. at the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (200-mhz device) provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. during the second clock, a subsequent oper ation (read/write/deselect) can be initiated. deselecting the device is also pipelined. therefore, when the sram is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. burst read accesses the CY7C1460AV25/cy7c1462av25/cy7c1464av25 have an on-chip burst count er that allows th e user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read access section above. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, an d will wrap-around when incre- mented sufficiently. a high input on adv/ld will increment the internal burst counter r egardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated w hen the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to the address inputs is loaded into the address register. the write signals are latched into the control logic block. on the subsequent clock rise the data lines are automatically three-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dq and dqp (dq a,b,c,d,e,f,g,h /dqp a,b,c,d,e,f,g,h for cy7c1464av25, dq a,b,c,d /dqp a,b,c,d for CY7C1460AV25 and dq a,b /dqp a,b for cy7c1462av25). in addition, the address for the subse- quent access (read/write/deselect) is latched into the address register (provided the appropriate control signals are asserted). on the next clock rise the data presented to dq and dqp (dq a,b,c,d,e,f,g,h /dqp a,b,c,d,e,f,g,h for cy7c1464av25, dq a,b,c,d /dqp a,b,c,d for CY7C1460AV25 and dq a,b /dqp a,b for cy7c1462av25) (or a subset for byte write operations, see write cycle description table for details) inputs is latched into the device and the write is complete. the data written during the writ e operation is controlled by bw (bw a,b,c,d,e,f,g,h for cy7c1464av25, bw a,b,c,d for CY7C1460AV25 and bw a,b for cy7c1462av25) signals. the CY7C1460AV25/cy7c1462av25/cy7c1464av25 provides byte write capability that is described in the write cycle description table. asserting the write enable input (we ) with the selected byte write select (bw ) input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. because the CY7C1460AV25/cy7c1462av25/cy7c1464av25 are common i/o devices, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high befor e presenting data to the dq and dqp (dq a,b,c,d,e,f,g,h /dqp a,b,c,d,e,f,g,h for cy7c1464av25, dq a,b,c,d /dqp a,b,c,d for CY7C1460AV25 and dq a,b /dqp a,b for cy7c1462av25) inputs. doing so will three-state the output drivers. as a safety precaution, dq and dqp (dq a,b,c,d,e,f,g,h /dqp a,b,c,d,e,f,g,h for cy7c1464av25, dq a,b,c,d /dqp a,b,c,d for CY7C1460AV25 and dq a,b /dqp a,b for cy7c1462av25) are automatically three-stated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the CY7C1460AV25/cy7c1462av25/cy7c1464av25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write opera- tions without reasserting the address inputs. adv/ld must be driven low in order to load t he initial address, as described in the single write access section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bw (bw a,b,c,d,e,f,g,h for
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 8 of 27 CY7C1460AV25, bw a,b,c,d for CY7C1460AV25 and bw a,b for cy7c1462av25) inputs must be driven in each cycle of the burst write in order to writ e the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, da ta integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address second address third address fourth address a1,a0 a1,a0 a1,a0 a1,a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address second address third address fourth address a1,a0 a1,a0 a1,a0 a1,a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 100 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current t his parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep curre nt this parameter is sampled 0 ns truth table [1, 2, 3, 4, 5, 6, 7] operation address used ce zz adv/ld we bw x oe cen clk dq deselect cycle none h l l x x x l l-h tri-state continue deselect cycle none x l h x x x l l-h tri-state read cycle (begin burst) external l l l h x l l l-h data out (q) read cycle (continue burst) next x l h x x l l l-h data out (q) nop/dummy read (begin burst) external l l l h x h l l-h tri-state dummy read (continue burst) next x l h x x h l l-h tri-state write cycle (begin burst) external l l l l l x l l-h data in (d) write cycle (continue burst) next x l h x l x l l-h data in (d) nop/write abort (begin burst) none l l l l h x l l-h tri-state write abort (continue burst) next x l h x h x l l-h tri-state ignore clock edge (stall) current x l x x x x h l-h ? sleep mode none x h x x x x x x tri-state notes: 1. x = ?don't care?, h = logic high, l = logic low, ce stands for all chip enables active. bw x = l signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 2. write is defined by we and bw x . see write cycle description table for details. 3. when a write cycle is detected, all i/os are tri-stated, even during byte writes. 4. the dq and dqp pins are controlled by the current cycle and the oe signal. 5. cen = h inserts wait states. 6. device will power-up deselected and the i/os in a tri-state condition, regardless of oe . 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles.during a read cycle dq s and dqp x = three-state when oe is inactive or when the device is deselected, and dq s =data when oe is active.
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 9 of 27 partial write cycle description [1, 2, 3, 8] function (CY7C1460AV25) we bw d bw c bw b bw a read h x x x x write ? no bytes written l h h h h write byte a ? (dq a and dqp a ) lhhhl write byte b ? (dq b and dqp b )lhhlh write bytes b, a l h h l l write byte c ? (dq c and dqp c )lhlhh write bytes c, a l h l h l write bytes c, b l h ll l h write bytes c, b, a l h l l l write byte d ? (dq d and dqp d )llhhh write bytes d, a l l h h l write bytes d, b llhlh write bytes d, b, a l l h l l write bytes d, c l l l h h write bytes d, c, a l l l h l write bytes d, c, b l l l l h write all bytes l l l l l function (cy7c1462av25) we bw b bw a read h x x write ? no bytes written l h h write byte a ? (dq a and dqp a )lhl write byte b ? (dq b and dqp b )llh write both bytes l l l function (cy7c1464av25) we bw x read hx write ? no bytes written l h write byte x ? (dq x and dqp x) ll write all bytes lall bw = l note: 8. table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write will be done based on which byte write is active.
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 10 of 27 ieee 1149.1 serial boundary scan (jtag) the CY7C1460AV25/cy7c1462av25/cy7c1464av25 incor- porates a serial boundary scan test access port (tap). this part is fully compliant with 1149.1. the tap operates using jedec-standard 2.5v/1.8v i/o logic level. the CY7C1460AV25/cy7c1462av25/cy7c1464av25 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low(v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alter- nately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. tap controller state diagram the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signif- icant bit (msb) of any regist er. (see tap controller block diagram.) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram.) tap controller block diagram performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck t ms tap controller tdi td o
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 11 of 27 when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the length of the boundary scan register for the sram in different packages is listed in the scan register sizes table. the boundary scan register is lo aded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr st ate. the sample z command puts the output bus into a high-z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1-mandatory instruction. when the sample/preload instruct ions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the ta p may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guar antee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/p reload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system out put pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates that t he tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit #89 (for 165-fbga package) or bit #138 (for 209 fbga package).
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 12 of 27 when this scan cell, called the ?extest output bus tri-state,? is latched into the preload register during the ?update-dr? state in the tap controller, it will directly control the state of the output (q-bus) pins, when t he extest is entered as the current instruction. when high, it will enable the output buffers to drive the output bus. when low, this bit will place the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? stat e. during ?update-dr,? the value loaded into that shift-register cell will latch into the preload register. when the extest instru ction is entered, this bit will directly control the output q-bu s pins. note that this bit is preset high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined tap ac switching characteristics over the operating range [9, 10] parameter description min. max. unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 20 ns t tl tck clock low time 20 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns set-up times t tmss tms set-up to tck clock rise 5 ns t tdis tdi set-up to tck clock rise 5 ns t cs capture set-up to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns notes: 9. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. test conditions are specified using t he load in tap ac test conditions. t r /t f = 1 ns.
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 13 of 27 2.5v tap ac test conditions input pulse levels ........... .................................... v ss to 2.5v input rise and fall time .......... .......................................... 1 ns input timing reference levels .........................................1.25v output reference levels.................................................1.25v test load termination supply vo ltage.............................1.25v 2.5v tap ac output load equivalent 1.8v tap ac test conditions input pulse levels.............. ....................... 0.2v to v ddq ? 0.2 input rise and fall time .....................................................1 ns input timing reference levels...... ..................................... 0.9v output reference levels ............. ..................................... 0.9v test load termination supply vo ltage .............................. 0.9v 1.8v tap ac output load equivalent t do 1.25v 20p f z = 50 ? o 50 ? t do 0.9v 20p f z = 50 ? o 50 ? tap dc electrical characteristics and operating conditions (0c < ta < +70c; v dd = 2.5v 0.125v unless otherwise noted) [11] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ?1.0 ma v ddq = 2.5v 1.7 v v oh2 output high voltage i oh = ?100 av ddq = 2.5v 2.1 v v ddq = 1.8v 1.6 v v ol1 output low voltage i ol = 1.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 av ddq = 2.5v 0.2 v v ddq = 1.8v 0.2 v v ih input high voltage v ddq = 2.5v 1.7 v dd + 0.3 v v ddq = 1.8v 1.26 v dd + 0.3 v v il input low voltage v ddq = 2.5v ?0.3 0.7 v v ddq = 1.8v ?0.3 0.36 v i x input load current gnd v i v ddq ?5 5 a identification register definitions instruction field CY7C1460AV25 (1m 36) cy7c1462av25 (2m 18) cy7c1464av25 (512k 72) description revision number (31:29) 000 000 000 describes the version number device depth (28:24) 01011 01011 01011 reserved for internal use architecture/memory type(23:18) 001000 00100 0 001000 defines memory type and archi- tecture bus width/density(17:12) 100111 010111 110111 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 00000110100 allows unique identification of sram vendor id register presence indicator (0) 1 1 1 indicates the presence of an id register note: 11. all voltages referenced to v ss (gnd).
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 14 of 27 scan register sizes register name bit size (x36) bit size (x18) bit size (x72) instruction 3 3 3 bypass 1 1 1 id 32 32 32 boundary scan order (165-ball fbga package) 89 89 ? boundary scan order (209-ball fbga package) ? ? 138 identification codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. plac es the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. pl aces the boundary scan regi ster between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 15 of 27 165-ball fbga boundary scan order [12] CY7C1460AV25 (1m x 36), cy7c1462av25 (2m x 18) bit# ball id bit# ball id bit# ball id bit# ball id 1n6 26e11 51a3 76n1 2n7 27d11 52a2 77n2 3n10 28g10 53b2 78p1 4p11 29f10 54c2 79r1 5 p8 30 e10 55 b1 80 r2 6 r8 31 d10 56 a1 81 p3 7r9 32c11 57c1 82r3 8p9 33a11 58d1 83p2 9p10 34b11 59e1 84r4 10 r10 35 a10 60 f1 85 p4 11 r11 36 b10 61 g1 86 n5 12 h11 37 a9 62 d2 87 p6 13 n11 38 b9 63 e2 88 r6 14 m11 39 c10 64 f2 89 internal 15 l11 40 a8 65 g2 16 k11 41 b8 66 h1 17 j11 42 a7 67 h3 18 m10 43 b7 68 j1 19 l10 44 b6 69 k1 20 k10 45 a6 70 l1 21 j10 46 b5 71 m1 22 h9 47 a5 72 j2 23 h10 48 a4 73 k2 24 g11 49 b4 74 l2 25 f11 50 b3 75 m2 note: 12. bit# 89 is preset high.
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 16 of 27 209-ball fbga boundary scan order [12, 13] cy7c1464av25 (512k x 72) bit# ball id bit# ball id bit# ball id bit# ball id 1 w6 36 f6 71 h6 106 k3 2 v6 37 k8 72 c6 107 k4 3 u6 38 k9 73 b6 108 k6 4 w7 39 k10 74 a6 109 k2 5v7 40j11 75a5 110l2 6 u7 41 j10 76 b5 111 l1 7t7 42h11 77c5 112m2 8 v8 43 h10 78 d5 113 m1 9 u8 44 g11 79 d4 114 n2 10 t8 45 g10 80 c4 115 n1 11 v9 46 f11 81 a4 116 p2 12 u9 47 f10 82 b4 117 p1 13 p6 48 e10 83 c3 118 r2 14 w11 49 e11 84 b3 119 r1 15 w10 50 d11 85 a3 120 t2 16 v11 51 d10 86 a2 121 t1 17 v10 52 c11 87 a1 122 u2 18 u11 53 c10 88 b2 123 u1 19 u10 54 b11 89 b1 124 v2 20 t11 55 b10 90 c2 125 v1 21 t10 56 a11 91 c1 126 w2 22 r11 57 a10 92 d2 127 w1 23 r10 58 c9 93 d1 128 t6 24 p11 59 b9 94 e1 129 u3 25 p10 60 a9 95 e2 130 v3 26 n11 61 d8 96 f2 131 t4 27 n10 62 c8 97 f1 132 t5 28 m11 63 b8 98 g1 133 u4 29 m10 64 a8 99 g2 134 v4 30 l11 65 d7 100 h2 135 w5 31 l10 66 c7 101 h1 136 v5 32 k11 67 b7 102 j2 137 u5 33 m6 68 a7 103 j1 138 internal 34 l6 69 d6 104 k1 35 j6 70 g6 105 n6 note: 13. bit# 138 is preset high.
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 17 of 27 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v dd relative to gnd........ ?0.5v to +3.6v supply voltage on v ddq relative to gnd ...... ?0.5v to +v dd dc to outputs in tri-state ................... ?0.5v to v ddq + 0.5v dc input voltage....................................?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 2.5v ?5%/+5% 1.7v to v dd industrial ?40c to +85c electrical characteristics over the operating range [14, 15] dc electrical characteristics over the operating range parameter description test conditions min. max. unit v dd power supply voltage 2.375 2.625 v v ddq i/o supply voltage for 2.5v i/o 2.375 v dd v for 1.8v i/o 1.7 1.9 v v oh output high voltage for 2.5v i/o, i oh = ? 1.0 ma 2.0 v for 1.8v i/o, i oh = ?100 a1.6v v ol output low voltage for 2.5v i/o, i ol = 1.0 ma 0.4 v for 1.8v i/o, i ol = 100 a, 0.2 v v ih input high voltage [14] for 2.5v i/o 1.7 v dd + 0.3v v for 1.8v i/o 1.26 v dd + 0.3v v v il input low voltage [14] for 2.5v i/o ?0.3 0.7 v for 1.8v i/o ?0.3 0.36 v i x input leakage current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 4-ns cycle, 250 mhz 435 ma 5-ns cycle, 200 mhz 385 ma 6-ns cycle, 167 mhz 335 ma i sb1 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = f max = 1/t cyc all speed grades 185 ma i sb2 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speed grades 120 ma i sb3 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = f max = 1/t cyc all speed grades 160 ma i sb4 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = 0 all speed grades 135 ma notes: 14. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac)> ?2v (pulse width less than t cyc /2). 15. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd .
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 18 of 27 capacitance [16] parameter description test conditions 100 tqfp max. 165 fbga max. 209 fbga max. unit c in input capacitance t a = 25c, f = 1 mhz, v dd = 2.5v v ddq = 2.5v 6.5 7 5 pf c clk clock input capacitance 3 7 5 pf c i/o input/output capacitance 5.5 6 7 pf thermal resistance [16] parameters description test conditions 100 tqfp package 165 fbga package 209 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 25.21 20.8 25.31 c/w jc thermal resistance (junction to case) 2.58 3.2 4.48 c/w ac test loads and waveforms note: 16. tested initially and after any design or process change that may affect these parameters. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) 3.3v i/o test load 2.5v i/o test load
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 19 of 27 switching characteristics over the operating range [21, 22] parameter description ?250 ?200 ?167 unit min. max. min. max. min. max. t power [17] v cc (typical) to the first access read or write 1 1 1 ms clock t cyc clock cycle time 4.0 5.0 6.0 ns f max maximum operating frequency 250 200 167 mhz t ch clock high 1.5 2.0 2.4 ns t cl clock low 1.5 2.0 2.4 ns output times t co data output valid after clk rise 2.6 3.2 3.4 ns t eov oe low to output valid 2.6 3.0 3.4 ns t doh data output hold after clk rise 1.0 1.5 1.5 ns t chz clock to high-z [18, 19, 20] 2.6 3.0 3.4 ns t clz clock to low-z [18, 19, 20] 1.0 1.3 1.5 ns t eohz oe high to output high-z [18, 19, 20] 2.6 3.0 3.4 ns t eolz oe low to output low-z [18, 19, 20] 000ns set-up times t as address set-up before clk rise 1.2 1.4 1.5 ns t ds data input set-up before clk rise 1.2 1.4 1.5 ns t cens cen set-up before clk rise 1.2 1.4 1.5 ns t wes we , bw x set-up before clk rise 1.2 1.4 1.5 ns t als adv/ld set-up before clk rise 1.2 1.4 1.5 ns t ces chip select set-up 1.2 1.4 1.5 ns hold times t ah address hold after clk rise 0.3 0.4 0.5 ns t dh data input hold after clk rise 0.3 0.4 0.5 ns t cenh cen hold after clk rise 0.3 0.4 0.5 ns t weh we , bw x hold after clk rise 0.3 0.4 0.5 ns t alh adv/ld hold after clk rise 0.3 0.4 0.5 ns t ceh chip select hold after clk rise 0.3 0.4 0.5 ns notes: 17. this part has a voltage regulator internally; t power is the time power needs to be supplied above v dd minimum initially, before a read or write operation can be initiated. 18. t chz , t clz , t eolz , and t eohz are specified with ac test conditions shown in (b) of ac test loads. transition is measured 200 mv from steady-state voltage . 19. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not impl y a bus contention condition, but reflect pa rameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 20. this parameter is sampled and not 100% tested. 21. timing reference is 1.25v when v ddq = 2.5v and 0.9v when v ddq = 1.8v. 22. test conditions shown in (a) of ac test loads unless otherwise noted.
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 20 of 27 switching waveforms read/write/timing [23, 24, 25] nop, stall and deselect cycles [23, 24, 26] notes: 23. for this waveform zz is tied low. 24. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high,ce 1 is high or ce 2 is low or ce 3 is high. 25. order of the burst sequence is determined by the status of th e mode (0=linear, 1=interleaved).burst operations are optional. 26. the ignore clock edge or stall cycle (clock 3) illustrated cen being used to create a pause. a wr ite is not perform ed during this cycle. write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds data i n-out (dq) t clz d(a1) d(a2) d(a5) q(a4) q(a3) d(a2+1) t doh t chz t co write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz t doh don?t care undefined q(a6) q(a4+1) read q(a3) 456 78910 clk ce we cen bwx adv/ld address a3 a4 a5 d(a4) data in-out (dq) a1 q(a5) write d(a4) stall write d(a1) 123 read q(a2) stall nop read q(a5) deselect continue deselect don?t care undefined t chz a2 d(a1) q(a2) q(a3)
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 21 of 27 zz mode timing [27, 28] notes: 27. device must be deselected when entering zz mode. see cycle descr iption table for all possible signal conditions to deselect the device. 28. i/os are in high-z when exiting zz sleep mode. switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 22 of 27 ordering information not all of the speed, package and temperature ranges ar e available. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram part and package type operating range 167 CY7C1460AV25-167axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1462av25-167axc CY7C1460AV25-167bzc 51-85165 165-ball fine-p itch ball grid array (15 x 17 x 1.4 mm) cy7c1462av25-167bzc CY7C1460AV25-167bzxc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1462av25-167bzxc cy7c1464av25-167bgc 51-85167 209-ball fine-pitch ball grid array (14 22 1.76 mm) cy7c1464av25-167bgxc 209-ball fine-pitch ball grid array (14 22 1.76 mm) lead-free CY7C1460AV25-167axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free lndustrial cy7c1462av25-167axi CY7C1460AV25-167bzi 51-85165 165-ball fine-p itch ball grid array (15 x 17 x 1.4 mm) cy7c1462av25-167bzi CY7C1460AV25-167bzxi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1462av25-167bzxi cy7c1464av25-167bgi 51-85167 209-ball fine-pitch ball grid array (14 22 1.76 mm) cy7c1464av25-167bgxi 209-ball fine-pitch ball grid array (14 22 1.76 mm) lead-free 200 CY7C1460AV25-200axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1462av25-200axc CY7C1460AV25-200bzc 51-85165 165-ball fine-p itch ball grid array (15 x 17 x 1.4 mm) cy7c1462av25-200bzc CY7C1460AV25-200bzxc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1462av25-200bzxc cy7c1464av25-200bgc 51-85167 209-ball fine-pitch ball grid array (14 22 1.76 mm) cy7c1464av25-200bgxc 209-ball fine-pitch ball grid array (14 22 1.76 mm) lead-free CY7C1460AV25-200axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free lndustrial cy7c1462av25-200axi CY7C1460AV25-200bzi 51-85165 165-ball fine-p itch ball grid array (15 x 17 x 1.4 mm) cy7c1462av25-200bzi CY7C1460AV25-200bzxi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1462av25-200bzxi cy7c1464av25-200bgi 51-85167 209-ball fine-pitch ball grid array (14 22 1.76 mm) cy7c1464av25-200bgxi 209-ball fine-pitch ball grid array (14 22 1.76 mm) lead-free
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 23 of 27 250 CY7C1460AV25-250axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1462av25-250axc CY7C1460AV25-250bzc 51-85165 165-ball fine-p itch ball grid array (15 x 17 x 1.4 mm) cy7c1462av25-250bzc CY7C1460AV25-250bzxc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1462av25-250bzxc cy7c1464av25-250bgc 51-85167 209-ball fine-pitch ball grid array (14 22 1.76 mm) cy7c1464av25-250bgxc 209-ball fine-pitch ball grid array (14 22 1.76 mm) lead-free CY7C1460AV25-250axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free industrial cy7c1462av25-250axi CY7C1460AV25-250bzi 51-85165 165-ball fine-p itch ball grid array (15 x 17 x 1.4 mm) cy7c1462av25-250bzi CY7C1460AV25-250bzxi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1462av25-250bzxi cy7c1464av25-250bgi 51-85167 209-ball fine-pitch ball grid array (14 22 1.76 mm) cy7c1464av25-250bgxi 209-ball fine-pitch ball grid array (14 22 1.76 mm) lead-free ordering information (continued) not all of the speed, package and temperature ranges ar e available. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram part and package type operating range
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 24 of 27 package diagrams note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 100-pin tqfp (14 x 20 x 1.4 mm) (51-85050) 51-85050-*b
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 25 of 27 package diagrams (continued) a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.450.05(165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.35 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.05 -0.10 165-ball fbga (15 x 17 x 1.4 mm) (51-85165) 51-85165-*a
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 26 of 27 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. zbt is a registered trademark of integrated device technology, inc. no bu s latency and nobl are trademarks of cypress semiconductor corporation. all product and company names ment ioned in this document are trademarks of their respective holders. package diagrams (continued) 209-ball fbga (14 x 22 x 1.76 mm) (51-85167) 51-85167-**
CY7C1460AV25 cy7c1462av25 cy7c1464av25 document #: 38-05354 rev. *d page 27 of 27 document history page document title: CY7C1460AV25/cy7c1462av25/cy7c1464av25 36 -mbit (1-mbit x 36/2-mbit x 18/512k x 72) pipelined sram with nobl? architecture document number: 38-05354 rev. ecn no. issue date orig. of change description of change ** 254911 see ecn syt new data sheet part number changed from previous revision (new and old part number differ by the letter ?a?) *a 303533 see ecn syt changed h9 pin from v ssq to v ss on the pin configuration table for 209 fbga on page # 5 changed the test condition from v dd = min. to v dd = max for v ol in the electrical characteristics table replaced ja and jc from tbd to respective thermal values for all packages on the therma l resistance table changed i dd from 450, 400 & 350 ma to 435, 385 & 335 ma for 250, 200 and 167 mhz respectively changed i sb1 from 190, 180 and 170 ma to 185 ma for 250, 200 and 167 mhz respectively changed i sb2 from 80 ma to 100 ma for all frequencies changed i sb3 from 180, 170 & 160 ma to 160 ma for 250, 200 and 167 mhz respectively changed i sb4 from 100 ma to 110 ma for all frequencies changed c in , c clk and c i/o to 6.5, 3 and 5.5 pf from 5, 5 and 7 pf for tqfp package changed t co from 3.0 to 3.2 ns and t doh from 1.3 ns to 1.5 ns for 200 mhz speed bin added lead-free information for 100 tqfp, 165 fbga and 209 fbga packages *b 331778 see ecn syt modified address expansion balls in the pinouts for 165 fbga and 209 fbga package as per jedec standar ds and updated the pin definitions accordingly modified v ol, v oh test conditions changed c in , c clk and c i/o to 7, 7and 6 pf from 5, 5 and 7 pf for 165 fbga package added industrial temperature grade changed i sb2 and i sb4 from 100 and 110 ma to 120 and 135 ma respec- tively updated the ordering information by shading and unshading mpns as per availability *c 417547 see ecn rxu converted from preliminary to final changed address of cypress semicond uctor corporation on page# 1 from ?3901 north first street? to ?198 champion court? modified test condition from v ddq < v dd to v ddq v dd changed i x current value in mode from ?5 & 30 a to ?30 & 5 a respec- tively and also changed i x current value in zz from ?30 & 5 a to ?5 & 30 a respectively on page# 19 modified ?input load? to ?input leak age current except zz and mode? in the electrical characteristics table replaced package name column with package diagram in the ordering information table replaced package diagram of 51-85050 from *a to *b *d 473650 see ecn vkn added the maximum rating for supply voltage on v ddq relative to gnd. changed t th , t tl from 25 ns to 20 ns and t tdov from 5 ns to 10 ns in tap ac switching characteristics table. updated the ordering information table.

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